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vb nc h1 l1 w1 rst clk gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v cc nc s out w0 h0 l0 c out dq 16 - pin so (300 - mil) see mech. drawings section features two dig it ally contro ll ed, 256-pos iti on poten ti omet er s s er ial port provides means for se tti ng and rea ding both poten ti omet er s resistors ca n be conn ec ted in s er ies to provide in cr eased total re sistance 16-pin so and 20-pin t ss op p ac kages resis ti ve elements are temp era tu re compensated to 0.3 lsb re la ti ve li n ear ity stand ar d re sistance values: C ds1267b-10 ~ 10k ? C ds1267b-50 ~ 50k ? C ds1267b-100 ~ 100k ? op era ti ng temp era ture range: C industria l: -40c to +85c pin descriptions l0, l1 - low end of resistor h0, h1 - high end of resistor w0, w1 - wiper terminal of resistor v b - substrate bias voltage s out - stacked configuration output rst - serial port reset input dq - serial port data input clk - serial port clock input c out - cascade port output v cc - +5v supply gnd - ground nc - no internal connection pin assignment part no. pin - package end - to - end resistance (k?) ds1267be - 010+ 20 tssop 10 ds1267be - 050+ 20 tssop 50 ds1267be - 100+ 20 tssop 100 ds1267bs - 010+ 16 so 10 ds1267bs - 050+ 16 so 50 ds1267bs - 100+ 16 so 100 ds1267b dual digital potentiometer 20 - pin tssop (173 - mil) vb nc h1 l1 w1 rst clk 20 19 18 17 16 15 14 1 2 3 4 5 6 7 v cc nc nc s out w0 h0 l0 8 9 10 13 12 11 c out nc nc nc gnd dq 19 - 65 89 ; rev 1 ; 1 /1 4 maxim integrated 1 downloaded from: http:///
ds1267b description the ds1267b dual digital potentiometer chip consists of two digitally controlle d, solid - state potentiometers. each potentiometer is composed of 256 resistive sections. between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. the position of the wiper on the resistive array is set by an 8 - bit value that controls which tap point is connected to the wiper output. communication and control of the device are accomplished via a 3 - wire serial port interfac e. this interface allows the device wiper position to be read or written. both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. for multiple - device, single - processor environments, the ds1 267b can be cascaded or daisy -chained. this feature provides for control of multiple devices over a single 3-wi re bus. the ds1267b is offered in three standard resistance values which include 10 k ? , 50 k ? , and 100 k ? versions. available packages for the device include a 16 -pin so and 20- pin tssop. operation the ds1267b contains two 256 - position potentiometers whose wiper positions are set by an 8 - bit value. these two 8 - bit values are written to a 17 - bit i/o shift register that is used to store the two wi per positions and the stack select bit when the device is powered. a block diagram of the ds1267b is presented in figure 1. communication and control of the ds1267b are accomplished through a 3 - wire serial port interface that drives an internal control logic unit. the 3 - wire serial interface consists of the three input signals: rst , clk, and dq. the rst control signal is used to enable the 3 - wire serial port operation of the device. the chip is selected when rst is high; rst must be high to begin any communication to the ds1267b. the clk signal input is used to provide timing synchronization for data input and output. the dq sig nal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17 - bit i/o shift register of the ds1267b. figure 9(a) presents the 3 - wire serial port protocol. as shown, the 3 - wire port is inactive when the rst signal input is low. communication with the ds1267b requires the transition of the rst input from a low state to a high state. once the 3 - wire port has been activated, data is entered into the part on the low to high transition of the clk signal inputs. three - wire serial t iming requirements are provided in the timing diagrams of figure 9(b) - (c). data written to the ds1267b over the 3 - wire serial interface is stored in the 17 - bit i/o shift register (see figure 2). the 17 - bit i/o shift register contains both 8 - bit potentiome ter wiper position values and the stack select bit. the composition of the i/o shift register is presented in fig ure 2. bit 0 of the i/o shift register contains the stack select bit, which will be discussed in the section entitle d stacked configuration . bi ts 1 through 8 of the i/o shift register contain the potentiometer - 1 wiper position value. bit 1 contains the msb of the wiper setting for potentiometer - 1 and bit 8 the lsb for the wiper setting. bits 9 through 16 of the i/o shift register contain the value of the potentiometer -0 wiper position, with the msb for the wiper position occupying bit 9 and the lsb bit 16. downloaded from: http:///
ds1267b ds1267b block diagram figure 1 i/o shift register figure 2 transmission of data always begins with the stack select bit followed by the pote ntiometer - 1 wiper position value and lastly the potentiometer-0 wiper position value. when wiper position data is to be written to the ds1267b, 17 bits (or some integer mul tiple) of data should always be transmitted. transactions which do not send a complete 17 bits (or multi ple) will leave the register incomplete and possibly an error in the desired wiper positions. after a communication transaction has been completed, t he rst signal input should be taken to a low state to prevent any inadvertent changes to the device shift register. once rst has reached a low state, the contents of the i/o shift register are loaded into the respective multiplexers for setting wiper position. a new wiper position will only engage after a rst transition to the inactive state. on device power - up the ds1267b wiper positions will be set at 50% of the total resistance or binary value 1000 0000. maxim integra ted ............................................................................................................................................................................................. 3 downloaded from: http:///
ds1267b stacked configuration the potentiometers of the ds1267b can be connected in series as shown in figure 3. this i s referred to as the stacked configuration. the stacked configuration allows the user to double the tot al end - to - end resistance of the part and the number of steps to 512 (or 9 bits of resolution). the wiper output for the combined stacked potentiometer will be taken at the s out pin, which is the multiplexed output of the wiper of potentiometer - 0 (w0) or potentiometer - 1 (w1). the potenti ometer wiper selected at the s out output is governed by the setting of the stack select bit (bit 0) of the 17 - bit i/o shift register. if the stack select bit has value 0, the multiplexed output, s out , will be that of the potentiometer - 0 wiper. if the stack select bit has value 1, the multiplexed output, s out , will be that of the potentiometer -1 wiper. stacked configuration figure 3 cascade operation a feature of the ds1267b is the ability to control multiple devices from a single processor. multiple ds 1267bs can be linked or daisy - chained as shown in figure 4. as a data bit is entered into the i/o shift register of the ds1267b a bit will appear at the c out output within a maximum delay of 50 nanoseconds. the stack select bit of the ds1267b will always b e the first out the part at the beginning of a transaction. additionally the c out pin is always active regardless of the state of rst . this allows one to read the i/o shift register without changing its value. cascading multiple devices figure 4 maxim integra ted ............................................................................................................................................................................................. 4 downloaded from: http:///
ds1267b the c out output of the ds1267b can be used to drive the dq input of another ds1267b. when connecting multiple devices, the total number of bits transmitted is always 17 times the number of ds1267bs in the daisy chain. an optional feedback resistor can be placed between the c out terminal of the last device and the first ds1267b dq input, thus allowing the controlling processor to read as well as write dat a or circularly clock data through the daisy chain. the value of the feedback or isolation resistor should be in the range from 2 ? to 10k ? . when reading data via the c out pin and isolation resistor, the dq line is left floating by the reading device. when rst is driven high, bit 17 is present on the c out pin, which is fed back to the input dq pin through the isolation resistor. when the clk input transitions low to high, bit 17 is loaded int o the first position of the i/o shift register and bit 16 becomes present on c out and dq of the next device. after 17 bits (or 17 times the number of ds1267bs in the daisy chain), the data has shifted complet ely around and back to its original position. when rst transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded into the wiper - 0, wiper -1, and stack select bit i/o register. absolute and relative linearity absolute linearity, also known as integral nonlinearity, is defined as the differen ce between the actual measured output voltage and the expected output voltage. figure 5 presents the test circuit used to measure absolute linearity. absolute linearity is given in terms of a minimum incremen t or expected output when the wiper is moved one position. in the case of the test circuit, a minimum incre ment (mi) or one lsb would equal 10/512 volts. the equation for absolute linearity is given as follows: (1) absolute linearity (inl) al={v o (actual) - v o (expected)}/mi relative linearity, also known as differential nonlinearity, is a measu re of error between two adjacent wiper position points and is given in terms of mi by equation (2). (2) relative linearity (dnl) rl={v o (n+1) - v o (n)}/mi figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the ds1267b at 25c. the specification for absolute linearity of the ds1267b is 0.75 mi typical. the sp ecification for relative linearity of the ds1267b is 0.3 mi typical. maxim integra ted ............................................................................................................................................................................................. 5 downloaded from: http:///
ds1267b linearity measurement configuration figure 5 note: in this setup, a 2% delta in total resistance r0 to r1 would cause a 2.5 mi error. ds1267b absolute a nd relative linearity figure 6 typical application configurations figures 7 and 8 show two typical application configurations for the ds1267b. by c onnecting the wiper terminal of the part to a high - impedance load, the effects of the wiper resistance is minimized, since the wiper resistance can vary from 900 ? to 2000 ? dep ending on wiper voltage. figure 7 presents the device connected in an inverting variable gain amplifier. the gain of the circuit on figure 7 is g iven by the following equation: a v = -n/(255-n); where n = 0 to 255 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 lsb tap position linearity vs. tap position inl dnl ds 1267 b 10k maxim integra ted ............................................................................................................................................................................................. 6 downloaded from: http:///
ds1267b figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. note the resistance r1 is chosen to be much greater t han the wiper resistance to minimize its effect on circuit gain. inverting variable gain amplifier figure 7 fix gain attenuator figure 8 maxim integra ted ............................................................................................................................................................................................. 7 downloaded from: http:///
ds1267b absolute maximum ratings* voltage on any pin relative to ground (v b = gnd) .......................................................... -0.5v to +7.0v voltage on resistor pins when v b = -5.5v ............................................................... -5.5v to (v cc + 0.5v) voltage on v b .................................................................................................................................................................................. -5.5v to gnd operating temperature ........................................................................................................... -40 to +85c storage temperature .......................................................................................................... -55c to +125c soldering temperature ........................................................................................................... 260c for 10s * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure t o absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes supply voltage v cc 4.5 5.5 v 1 input logic 1 v ih 0.7 x v cc v cc + 0.5 v 1 input logic 0 v il -0.5 +0.3 x v cc v 1 substrate bias v b -5.5 gnd v 1 resistor inputs l,h,w v b - 0.5 v cc + 0.5 v 2 dc electrical characteristics (-40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes supply current i cc 2.1 5 ma 7 input leakage i li -1 +1 a 9 wiper resistance r w 900 2000 w wiper current i w 1 ma logic 1 output at 2.4v i oh -1 ma 5 logic 0 output at 0.4v i ol 4 ma 5 standby current i stby 0.6 2 a maxim integra ted ............................................................................................................................................................................................. 8 downloaded from: http:///
ds1267b analog resistor characteristics (-40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes end - to -end resistor tolerance -20 +20 % 8 integral nonlinearity (i nl) -1.6 .75 +1.6 lsb 3 differential nonlinearity (dnl) -0.5 0.3 +0.5 lsb 4 temperature coefficient 750 ppm/c capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf ac electrical characteristics (-40 c to +85 c; v cc = 5.0v 10%) parameter symbol min typ max units notes clk frequency f clk dc 3.5 mhz 6 width of clk pulse t ch 50 ns 6 data setup time t dc 30 ns 6 data hold time t cdh 10 ns 6 propagation delay time low to high level clock to output t plh 250 ns 6 propagation delay time high to low level t phl 250 ns 6 rst high to clock input high t cc 50 ns 6 rst low to clock input high t hlt 50 ns 6 rst inactive t rlt 125 ns 6 notes: 1. all voltages are referenced to ground. 2. resistor inputs cannot exceed the substrate bias voltage, v b , in the negative direction. 3. inl is used to determine wiper voltage versus expected voltage as determine d by wiper position. 4. dnl is used to determine the change in voltage between succes sive tap positions. 5. c out is active regardless of the state of rst . 6. see figure s 9(a), (b), and (c). 7. see figure 11. 8. valid at +25 c only. 9. digital inputs maxim integra ted ............................................................................................................................................................................................. 9 downloaded from: http:///
ds1267b timing diagrams figure 9 (a) 3 - wire serial interface general overview (b) start of communication transaction maxim integra ted ........................................................................................................................................................................................... 10 downloaded from: http:///
ds1267b (c) end of communication transaction typical supply curent vs. serial clock rate figure 11 maxim integra ted ........................................................................................................................................................................................... 11 downloaded from: http:///
ds1267b package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a di fferent suffix character, but the drawing pertains to the package regardless of rohs status . package type package code document no. land pattern no. 16 so w16+6 21 - 0042 90 - 0107 20 tssop u20+2 21 - 0066 90 - 0116 maxim integra ted ........................................................................................................................................................................................... 12 downloaded from: http:///
ds1267b revision history revision date description pages changed 1 /13 initial release 1/14 removed future product notation in ordering information 1 13 maxim integrated cannot assume responsibility for use of any circuitry other t han circuitry entirely embodied in a maxim integrated product. no circuit paten t licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max li mits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated, 160 rio robles, san jose, ca 95134 1 - 408 - 601 - 1000 201 4 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. downloaded from: http:///

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